DAC38RF86 Datasheet, PDF (44/141 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

DAC38RF86, DAC38RF87
DAC38RF97, DAC38RF96
SLASEF4 – FEBRUARY 2017
www.ti.com
8.3.16 JESD204B Pattern Test
The DAC38RFxx supports the following test patterns for JESD204B:
• Link layer test pattern by setting field JESD_TEST_SEQ in register JESD_LN_EN (8.5.45) and monitoring the
lane alarms (1 = fail, 0 = pass)
– Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)
– Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)
– Verify repeating initial lane alignment (ILA) sequence
• RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an
amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1, 2, 4 or 8. The
short test pattern has a duration of one frame period and is repeated continuously for the duration of the test.
Each sample has a unique value that can be identified with the position of the sample in the user data format.
The sample values are such that correct sample values will never be decoded at the receiver if there is a
mismatch between the mapping formats being used at the transmitter and receiver devices. This can
generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples
being transmitted. Refer to the JESD204B standard section 5.1.6 for more details.
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