DAC38RF86 Datasheet, PDF (31/141 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

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L-M-F-S-Hd
1 TX
12410
44210
24410
24310
L-M-F-S-
Hd
2 TX
24410
88210
48410
48310
Frame
Format
1 TX:
Table 15
2 TX:
Table 16
1 TX:
Table 17
2 TX:
Table 18
1 TX:
Table 19
2 TX:
Table 20
1 TX:
Table 21
2 TX:
Table 22
Input
Resolutio
n
16
16
16
16
16
16
16
16
12
IQ pairs
per DAC
1
1
2
2
2
2
2
2
2
Interp
16
24
8
12
16
24
16
24
DAC38RF86, DAC38RF87
DAC38RF97, DAC38RF96
SLASEF4 – FEBRUARY 2017
Input rate
max
(MSPS)
312.5
f_DAC Max DAC38RF86, DAC38RF96,
(MSPS) DAC38RF87 DAC38RF97
5000 x
x
312.5
7500 x
x
625
625
562.5
375
312.5
5000 x
7500 x
9000 x
9000 x
5000 x
312.5
7500 x
24
375
9000 x
Table 10. JESD204B Frame Format for LMFSHd = 82121
# un bits
# en bits
Nibble
lane RX0
lane RX1
lane RX2
lane RX3
lane RX4
lane RX5
lane RX6
lane RX7
4
8
5
10
1
2
i0[15:8]
i0[7:0]
i1[15:8]
i1[7:0]
q0[15:8]
q0[7:0]
q1[15:8]
q1[7:0]
Table 11. JESD204B Frame Format for LMFSHd = 42111
# un bits
# en bits
Nibble
lane RX0
lane RX1
lane RX2
lane RX3
4
8
5
10
1
2
i0[15:8]
i0[7:0]
q0[15:8]
q0[7:0]
Table 12. JESD204B Frame Format for LMFSHd = 84111
# un bits
# en bits
Nibble
lane RX0
lane RX1
lane RX2
lane RX3
lane RX4
lane RX5
lane RX6
4
8
5
10
1
2
i0[15:8]
i0[7:0]
q0[15:8]
q0[7:0]
i1[15:8]
i1[7:0]
q1[15:8]
Copyright © 2017, Texas Instruments Incorporated
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Product Folder Links: DAC38RF86 DAC38RF87 DAC38RF97 DAC38RF96