DAC38RF86 Datasheet, PDF(45/141 Page) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

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DAC38RF86 Datasheet, PDF (45/141 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

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DAC38RF86, DAC38RF87

DAC38RF97, DAC38RF96

SLASEF4 â FEBRUARY 2017

The DAC38RFxx expects the test samples, in a frame, transmitted by an logic device as per Table 33:

JESD Mode

82121

42111

22210

12410

44210

24410

41121

81180

24310

41380

Table 33. Short Test Patterns

7CB8, F431, 6DA9, E520

7CB8, F431

7CB8

7CB8, F431, 6DA9, E520

7C00, B800, F400, 3100, 6D00,

A900, E500, 2000, F800, 7100,

E900, 6200, DA00, 5300, CB00,

4000

87C0, F4B0

87C0, F4B0, D310, A960, 0E50,

F820, 9710, 62E0

7CB8, F431, 6DA9,

E520

6DA9, E520

6DA9

n/a

D310, A960

n/a

F871, E962

n/a

7CB8

n/a

0E50, F820

n/a

DA53, CB40

n/a

6DA9

n/a

9710, 62E0

n/a

The short test pattern has duration of one frame period and is repeated continuously for the duration of the test.

Each sample has a unique value that can be identified with the position of the sample in the user data format.

The sample values are such that correct sample values will never be decoded at the receiver if there is a

mismatch between the mapping formats being used at the transmitter and receiver devices. This can generally

be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted.

Following are the steps required to execute the short test functionality in DAC38RFxx.

1. Configure other registers, make sure clocks are up and running.

2. Start driving short test patterns

3. Clear short test alarm by writing â0â to field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP

(8.5.67). This is a paged register, one for each Multi-DUC.

4. Enable short test by writing a â1â to field SHORTTEST_ENA in register MULTIDUC_CFG2 (8.5.14).

5. Read the short test alarm from field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67).

This is a paged register, one for each Multi-DUC

If the alarm read from the register is high, the short test has detected an error.

8.3.17 Multiband DUC (multi-DUC)

Each DAC output in the DAC38RFxx is supported by a dual band digital upconverter (DUC), which is called a

multi-DUC.Figure 32 shows the signal processing features of each of the two multi-DUCs. The two paths are

identical and independent. The SPI interface registers for the multi-DUCs are addressed through paging, with

page 0 supporting multi-DUC1 and page 1 supporting multi-DUC2. Register PAGE_SET (8.5.8) is used to set the

pages. Both pages can be selected at the same time to program both multi-DUCs simultaneously with the same

settings.

Each multi-DUC has 2 DUC channels, called path AB and path CD. The output of one multi-DUC can be added

to the signal of the other multi-DUC to allow a configuration with 4 total DUCs summed together for 1 DAC. After

quadrature modulation is a sin(x)/x compensation filter, followed by the multiband summation block. The multi-

band summation block had the ability to add the signals from the other multi-DUC for a combined 4 DUCs, each

with independent frequency control. The final block is an output delay block with 0 â 15 sample range.

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