OMAPL137CZKBT3 Datasheet, PDF (95/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

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OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
6.11 External Memory Interface B (EMIFB)
Figure 6-20 illustrates a high-level view of the EMIFB and its connections within the device. Multiple
requesters have access to EMIFB through a switched central resource (indicated as crossbar in the
figure). The EMIFB implements a split transaction internal bus, allowing concurrence between reads and
writes from the various requesters.
EMIFB
CPU
EDMA
Master
Peripherals
(USB, UHPI...)
Crossbar
MPU2
Registers
EMB_CS
EMB_CAS
Cmd/Write
FIFO
EMB_RAS
EMB_WE
EMB_CLK
Read
FIFO
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
EMB_D[x:0]
EMB_WE_DQM[x:0]
SDRAM
Interface
Figure 6-20. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
6.11.1 EMIFB SDRAM Loading Limitations
EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads. Additional
loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by
board simulation using IBIS models.
Copyright © 2008–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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