OMAPL137CZKBT3 Datasheet, PDF (210/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
www.ti.com
6.31 IEEE 1149.1 JTAG
The JTAG ⁽¹⁾ interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
.TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
.RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
Table 6-116. DEVIDR0 Register
BYTE ADDRESS
0x01C1 4018
ACRONYM
REGISTER DESCRIPTION
DEVIDR0 JTAG Identification Register
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each
silicon revision is:
• 0x0B7D F02F for silicon revision 1.0
• 0x8B7D F02F for silicon revision 1.1
• 0x9B7D F02F for silicon revisions 3.0, 2.1, and 2.0
For the actual register bit names and their associated bit field descriptions, see Figure 6-73 and Table 6-
117.
Figure 6-73. JTAG ID (DEVIDR0) Register Description - Register Value
31
28 27
VARIANT
(4-bit)
PART NUMBER (16-bit)
R-xxxx
R-1011 1001 0110 1011
LEGEND: R = Read, W = Write, n = value at reset
12 11
MANUFACTURER (11-bit)
R-0000 0010 111
10
LSB
R-1
210 Peripheral Information and Electrical Specifications
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