OMAPL137CZKBT3 Datasheet, PDF (191/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

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OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
6.27.3 HPI Electrical Data/Timing
Table 6-101. Timing Requirements for Host-Port Interface Cycles^{(1) (2)}
No.
1
2
3
4
9
10
11
12
t_{su(SELV-HSTBL)}
t_{h(HSTBL-SELV)}
t_w(HSTBL)
t_w(HSTBH)
t_{su(SELV-HASL)}
t_h(HASL-SELV)
t_{su(HDV-HSTBH)}
t_h(HSTBH-HDV)
13 t_{h(HRDYL-HSTBH)}
PARAMETER
Setup time, select signals⁽³⁾ valid before UHPI_HSTROBE low
Hold time, select signals⁽³⁾ valid after UHPI_HSTROBE low
Pulse duration, UHPI_HSTROBE active low
Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses
Setup time, selects signals valid before UHPI_HAS low
Hold time, select signals valid after UHPI_HAS low
Setup time, host data valid before UHPI_HSTROBE high
Hold time, host data valid after UHPI_HSTROBE high
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE should
not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes will not
complete properly.
MIN MAX UNIT
5
ns
2
ns
15
ns
2M
ns
5
ns
2
ns
5
ns
2
ns
2
ns
16 t_{su(HASL-HSTBL)}
17 t_{h(HSTBL-HASH)}
Setup time, UHPI_HAS low before UHPI_HSTROBE low
Hold time, UHPI_HAS low after UHPI_HSTROBE low
2
ns
2
ns
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(2) M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns.
(3) Select signals include: UHPI_HCNTL[1:0], UHPI_HRW and UHPI_HHWIL.
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Peripheral Information and Electrical Specifications 191
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