OMAPL137CZKBT3 Datasheet, PDF (112/222 Pages) Texas Instruments – OMAP-L137 Low-Power Applications Processor

OMAP-L137
SPRS563G – SEPTEMBER 2008 – REVISED JUNE 2014
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BYTE
ADDRESS
0x01E2 3268
0x01E2 326C
0x01E2 3270
0x01E2 3274
0x01E2 3278
0x01E2 327C
0x01E2 3280
0x01E2 3284
0x01E2 3288
0x01E2 328C
Table 6-37. EMAC Statistics Registers (continued)
ACRONYM
FRAME64
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
REGISTER DESCRIPTION
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns Register
BYTE ADDRESS
0x01E2 2000
0x01E2 2004
0x01E2 200C
0x01E2 2010
0x01E2 2014
0x01E2 2018
0x01E2 201C
0x01E2 2020
0x01E2 2024
0x01E2 2028
0x01E2 202C
0x01E2 2030
0x01E2 2034
0x01E2 2038
0x01E2 203C
0x01E2 2040
0x01E2 2044
0x01E2 2048
0x01E2 204C
0x01E2 2050
0x01E2 2054
0x01E2 2058
0x01E2 205C
0x01E2 2060
0x01E2 2064
0x01E2 2068
0x01E2 206C
0x01E2 2070
0x01E2 2074
0x01E2 2078
0x01E2 207C
0x01E2 2080
0x01E2 2084
Table 6-38. EMAC Control Module Registers
ACRONYM
REV
SOFTRESET
INTCONTROL
C0RXTHRESHEN
C0RXEN
C0TXEN
C0MISCEN
C1RXTHRESHEN
C1RXEN
C1TXEN
C1MISCEN
C2RXTHRESHEN
C2RXEN
C2TXEN
C2MISCEN
C0RXTHRESHSTAT
C0RXSTAT
C0TXSTAT
C0MISCSTAT
C1RXTHRESHSTAT
C1RXSTAT
C1TXSTAT
C1MISCSTAT
C2RXTHRESHSTAT
C2RXSTAT
C2TXSTAT
C2MISCSTAT
C0RXIMAX
C0TXIMAX
C1RXIMAX
C1TXIMAX
C2RXIMAX
C2TXIMAX
REGISTER DESCRIPTION
EMAC Control Module Revision Register
EMAC Control Module Software Reset Register
EMAC Control Module Interrupt Control Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
112 Peripheral Information and Electrical Specifications
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