TM4C1237D5PM_15 Datasheet, PDF (944/1277 Pages) Texas Instruments – Tiva Microcontroller

Synchronous Serial Interface (SSI)
Register 2: SSI Control 1 (SSICR1), offset 0x004
The SSICR1 register contains bit fields that control various functions within the SSI module. Master
and slave mode functionality is controlled by this register.
SSI Control 1 (SSICR1)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x004
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EOT reserved MS
SSE
LBM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RO
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:5
4
3
2
Name
reserved
EOT
reserved
MS
Type
RO
RW
RO
RW
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
End of Transmission
This bit is only valid for Master mode devices and operations (MS = 0x0).
Value Description
0 The TXRIS interrupt indicates that the transmit FIFO is half full
or less.
1 The End of Transmit interrupt mode for the TXRIS interrupt is
enabled.
Note:
In Freescale SPI mode only, a condition can be created where
an EOT interrupt is generated for every byte transferred even
if the FIFO is full. If the EOT bit has been set to 0 in an
integrated slave SSI and the µDMA has been configured to
transfer data from this SSI to a Master SSI on the device using
external loopback, an EOT interrupt is generated by the SSI
slave for every byte even if the FIFO is full.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
SSI Master/Slave Select
This bit selects Master or Slave mode and can be modified only when
the SSI is disabled (SSE=0).
Value Description
0 The SSI is configured as a master.
1 The SSI is configured as a slave.
944
June 12, 2014
Texas Instruments-Production Data