TM4C1237D5PM_15 Datasheet, PDF (270/1277 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 20: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C
This register provides configuration information for the power control of the SRAM and Flash memory
while in Deep-Sleep mode.
Deep-Sleep Power Configuration (DSLPPWRCFG)
Base 0x400F.E000
Offset 0x18C
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FLASHPM
reserved
SRAMPM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RO
RO
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5:4
Name
reserved
FLASHPM
Type
RO
RW
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
Flash Power Modes
Value Description
0x0 Active Mode
Flash memory is not placed in a lower power mode. This mode
provides the fastest time to sleep and wakeup but the highest
power consumption while the microcontroller is in Deep-Sleep
mode.
0x1 Reserved
0x2 Low Power Mode
Flash memory is placed in low power mode. This mode provides
the lowers power consumption but requires more time to come
out of Deep-Sleep mode.
0x3 Reserved
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
270
June 12, 2014
Texas Instruments-Production Data