TM4C1237D5PM_15 Datasheet, PDF (814/1277 Pages) Texas Instruments – Tiva Microcontroller

Analog-to-Digital Converter (ADC)
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018
This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding
underflow condition is cleared by writing a 1 to the relevant bit position.
ADC Underflow Status (ADCUSTAT)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x018
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
UV3
UV2
UV1
UV0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW1C RW1C RW1C RW1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
UV3
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW1C
0
SS3 FIFO Underflow
The valid configurations for this field are shown below. This bit is cleared
by writing a 1.
Value Description
0 The FIFO has not underflowed.
1 The FIFO for the Sample Sequencer has hit an underflow
condition, meaning that the FIFO is empty and a read was
requested. The problematic read does not move the FIFO
pointers, and 0s are returned.
2
UV2
RW1C
0
SS2 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
1
UV1
RW1C
0
SS1 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
0
UV0
RW1C
0
SS0 FIFO Underflow
The valid configurations are the same as those for the UV3 field. This
bit is cleared by writing a 1.
814
June 12, 2014
Texas Instruments-Production Data