TM4C1237D5PM_15 Datasheet, PDF (751/1277 Pages) Texas Instruments – Tiva Microcontroller

12.1
Block Diagram
Figure 12-1. WDT Module Block Diagram
Interrupt/NMI
System Clock/
PIOSC
Control / Clock /
Interrupt
Generation
WDTCTL
WDTICR
WDTRIS
WDTMIS
WDTLOCK
WDTTEST
Tiva^™ TM4C1237D5PM Microcontroller
WDTLOAD
32-Bit Down
Counter
0x0000.0000
Comparator
WDTVALUE
Identification Registers
WDTPCellID0
WDTPCellID1
WDTPCellID2
WDTPCellID3
WDTPeriphID0 WDTPeriphID4
WDTPeriphID1 WDTPeriphID5
WDTPeriphID2 WDTPeriphID6
WDTPeriphID3 WDTPeriphID7
12.2
Functional Description
The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches
the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt.
The watchdog interrupt can be programmed to be a non-maskable interrupt (NMI) using the INTTYPE
bit in the WDTCTL register. After the first time-out event, the 32-bit counter is re-loaded with the
value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down
from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock
(WDTLOCK) register is written, which prevents the timer configuration from being inadvertently
altered by software.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled by setting the RESEN bit in the WDTCTL register, the Watchdog timer
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the
counter is loaded with the new value and continues counting.
June 12, 2014
751
Texas Instruments-Production Data