TM4C1237D5PM_15 Datasheet, PDF (545/1277 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1237D5PM Microcontroller
Bit/Field
1
0
Name
EREQ
START
Type
RO
RW
Reset
-
Description
Erase Required
Value Description
0 The copy buffer has available space.
1 An erase of the copy buffer is required.
0
Start Erase
Setting this bit starts error recovery if the PRETRY or ERETRY bit is set.
If both the PRETRY and the ERETRY bits are clear, setting this bit starts
erasing the copy buffer if EREQ is set. If none of the other bits in this
register are set, setting this bit is ignored. After this bit is set, the
WORKING bit in the EEDONE register is set and is cleared when the
operation is complete. In addition, the EEINT register can be used to
generate an interrupt on completion.
If this bit is set while an operation is in progress, the write is ignored.
The START bit is automatically cleared when the operation completes.
June 12, 2014
545
Texas Instruments-Production Data