TM4C1237D5PM_15 Datasheet, PDF (600/1277 Pages) Texas Instruments – Tiva Microcontroller

Micro Direct Memory Access (μDMA)
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C
Each bit of the DMAUSEBURSTCLR register represents the corresponding μDMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register.
DMA Channel Useburst Clear (DMAUSEBURSTCLR)
Base 0x400F.F000
Offset 0x01C
Type WO, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR[n]
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:0
Name
CLR[n]
Type
WO
Reset
-
Description
Channel [n] Useburst Clear
Value Description
0 No effect.
1 Setting a bit clears the corresponding SET[n] bit in the
DMAUSEBURSTSET register meaning that µDMA channel [n]
responds to single and burst requests.
600
June 12, 2014
Texas Instruments-Production Data