TM4C1237D5PM_15 Datasheet, PDF (938/1277 Pages) Texas Instruments – Tiva Microcontroller

Synchronous Serial Interface (SSI)
15.4
For the receive channel, a single transfer request is asserted whenever any data is in the receive
FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or
more items. For the transmit channel, a single transfer request is asserted whenever at least one
empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO
has 4 or more empty slots. The single and burst µDMA transfer requests are handled automatically
by the μDMA controller depending how the µDMA channel is configured.
To enable µDMA operation for the receive channel, the RXDMAE bit of the DMA Control
(SSIDMACTL) register should be set after configuring the µDMA. To enable µDMA operation for
the transmit channel, the TXDMAE bit of SSIDMACTL should be set after configuring the µDMA. If
µDMA is enabled, then the μDMA controller triggers an interrupt when a transfer is complete. The
interrupt occurs on the SSI interrupt vector. Therefore, if interrupts are used for SSI operation and
µDMA is enabled, the SSI interrupt handler must be designed to handle the μDMA completion
interrupt.
When transfers are performed from a FIFO of the SSI using the μDMA, and any interrupt is generated
from the SSI, the SSI module's status bit in the DMA Channel Interrupt Status (DMACHIS) register
must be checked at the end of the interrupt service routine. If the status bit is set, clear the interrupt
by writing a 1 to it.
See “Micro Direct Memory Access (μDMA)” on page 561 for more details about programming the
μDMA controller.
Initialization and Configuration
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module using the RCGCSSI register (see page 335).
2. Enable the clock to the appropriate GPIO module via the RCGCGPIO register (see page 329).
To find out which GPIO port to enable, refer to Table 21-5 on page 1220.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 647). To determine which GPIOs to
configure, see Table 21-4 on page 1215.
4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate
pins. See page 664 and Table 21-5 on page 1220.
5. Program the GPIODEN register to enable the pin's digital function. In addition, the drive strength,
drain select and pull-up/pull-down functions must be configured. Refer to “General-Purpose
Input/Outputs (GPIOs)” on page 625 for more information.
Note:
Pull-ups can be used to avoid unnecessary toggles on the SSI pins, which can take the
slave to a wrong state. In addition, if the SSIClk signal is programmed to steady state
High through the SPO bit in the SSICR0 register, then software must also configure the
GPIO port pin corresponding to the SSInClk signal as a pull-up in the GPIO Pull-Up
Select (GPIOPUR) register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
938
June 12, 2014
Texas Instruments-Production Data