LM4F111E5QR Datasheet, PDF (902/1114 Pages) Texas Instruments – Microcontroller

Synchronous Serial Interface (SSI)
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024
The SSIDMACTL register is the µDMA control register.
SSI DMA Control (SSIDMACTL)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
SSI2 base: 0x4000.A000
SSI3 base: 0x4000.B000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
18
17
16
RO
RO
RO
0
0
0
2
1
0
TXDMAE RXDMAE
RO
R/W
R/W
0
0
0
Bit/Field
31:2
1
Name
reserved
TXDMAE
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Transmit DMA Enable
Value Description
0 µDMA for the transmit FIFO is disabled.
1 µDMA for the transmit FIFO is enabled.
0
RXDMAE
R/W
0
Receive DMA Enable
Value Description
0 µDMA for the receive FIFO is disabled.
1 µDMA for the receive FIFO is enabled.
902
April 25, 2012
Texas Instruments-Advance Information