LM4F111E5QR Datasheet, PDF (391/1114 Pages) Texas Instruments – Microcontroller

Stellaris^® LM4F111E5QR Microcontroller
Register 102: Analog-to-Digital Converter Peripheral Ready (PRADC), offset
0xA38
The PRADC register indicates whether the ADC modules are ready to be accessed by software
following a change in status of power, Run mode clocking, or reset. A power change is initiated if
the corresponding PCADC bit is changed from 0 to 1. A Run mode clocking change is initiated if
the corresponding RCGCADC bit is changed. A reset change is initiated if the corresponding SRADC
bit is changed from 0 to 1.
The PRADC bit is cleared on any of the above events and is not set again until the module is
completely powered, enabled, and internally reset.
Analog-to-Digital Converter Peripheral Ready (PRADC)
Base 0x400F.E000
Offset 0xA38
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
R1
R0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
R1
Type
RO
R/W
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module 1 Peripheral Ready
Value Description
1 ADC module 1 is ready for access.
0 ADC module 1 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
0
R0
R/W
0
ADC Module 0 Peripheral Ready
Value Description
1 ADC module 0 is ready for access.
0 ADC module 0 is not ready for access. It is unclocked,
unpowered, or in the process of completing a reset sequence.
April 25, 2012
391
Texas Instruments-Advance Information