LM4F111E5QR Datasheet, PDF (134/1114 Pages) Texas Instruments – Microcontroller

Cortex-M4 Peripherals
Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110
Note: This register can only be accessed from privileged mode.
The EN4 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 128; bit 10 corresponds to Interrupt 138. See Table 2-9 on page 95 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 128-138 Set Enable (EN4)
Base 0xE000.E000
Offset 0x110
Type R/W, reset 0x0000.0000
31
30
29
28
27
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
15
14
13
12
11
reserved
Type RO
RO
RO
RO
RO
Reset
0
0
0
0
0
26
25
24
23
22
21
20
19
18
17
16
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
0
INT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:11
10:0
Name
reserved
INT
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0x0
Interrupt Enable
Value
0
1
Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS4 register.
134
April 25, 2012
Texas Instruments-Advance Information