LM4F111E5QR Datasheet, PDF (669/1114 Pages) Texas Instruments – Microcontroller

Stellaris^® LM4F111E5QR Microcontroller
Bit/Field
12
11:10
9
8
7
6
Name
reserved
TBEVENT
TBSTALL
TBEN
reserved
TAPWML
Type
RO
R/W
R/W
R/W
RO
R/W
Reset
0
0x0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
Note:
If PWM output inversion is enabled, edge detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger
has been set and the PWM inversion generates a postive
edge, no event-trigger interrupt asserts. Instead, the interrupt
is generated on the negative edge of the PWM signal.
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 Timer B continues counting while the processor is halted by the
debugger.
1 Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
GPTM Timer B Enable
The TBEN values are defined as follows:
Value Description
0 Timer B is disabled.
1 Timer B is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer A PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
April 25, 2012
669
Texas Instruments-Advance Information