LM4F111E5QR Datasheet, PDF(582/1114 Page) Texas Instruments – Microcontroller

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LM4F111E5QR Datasheet, PDF (582/1114 Pages) Texas Instruments – Microcontroller

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General-Purpose Input/Outputs (GPIOs)

register to the numeric encoding shown in the table below. Analog signals in the table below are

also 5-V tolerant and are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN)

register. The AINx analog signals have internal circuitry to protect them from voltages over VDD (up

to the maximum specified in Table 21-1 on page 1052), but analog performance specifications are

only guaranteed if the input signal swing at the I/O pad is kept inside the range 0 V < VIN < VDD.

Note that each pin must be programmed individually; no type of grouping is implied by the columns

in the table. Table entries that are shaded gray are the default values for the corresponding GPIO

pin.

Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,

GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0), with the exception of

the pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the

pins back to their default state.

Table 9-1. GPIO Pins With Non-Zero Reset Values

GPIO Pins

PA[1:0]

PA[5:2]

PB[3:2]

PC[3:0]

Default State

UART0

SSI0

I2C0

JTAG/SWD

GPIOAFSEL GPIODEN GPIOPDR GPIOPUR

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

GPIOPCTL

0x1

0x2

0x3

0x1

The GPIO commit control registers provide a layer of protection against accidental

programming of critical hardware signals including the GPIO pins that can function as

JTAG/SWD signals and the NMI signal. The commit control process must be followed

for these pins, even if they are programmed as alternate functions other than JTAG/SWD

or NMI, see âCommit Controlâ on page 588.

Table 9-2. GPIO Pins and Alternate Functions (64LQFP)

IO

Pin

Analog

Function

1

2

Digital Function (GPIOPCTL PMCx Bit Field Encoding)a

3

4

5

6

7

8

9

PA0 17

-

U0Rx

-

-

-

-

-

-

-

-

PA1 18

-

U0Tx

-

-

-

-

-

-

-

-

PA2 19

-

- SSI0Clk -

-

-

-

-

-

-

PA3 20

-

- SSI0Fss -

-

-

-

-

-

-

PA4 21

-

- SSI0Rx -

-

-

-

-

-

-

PA5 22

-

- SSI0Tx -

-

-

-

-

-

-

PA6 23

-

-

- I2C1SCL -

-

-

-

-

-

PA7 24

-

-

- I2C1SDA -

-

-

-

-

-

PB0 45

-

U1Rx

-

-

-

-

- T2CCP0 -

-

PB1 46

-

U1Tx

-

-

-

-

- T2CCP1 -

-

PB2 47

-

-

- I2C0SCL -

-

- T3CCP0 -

-

PB3 48

-

-

- I2C0SDA -

-

- T3CCP1 -

-

PB4 58 AIN10

- SSI2Clk -

-

-

- T1CCP0 CAN0Rx -

PB5 57 AIN11

- SSI2Fss -

-

-

- T1CCP1 CAN0Tx -

PB6 1

-

- SSI2Rx I2C5SCL -

-

- T0CCP0 -

-

PB7 4

-

- SSI2Tx I2C5SDA -

-

- T0CCP1 -

-

14

15

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

582

April 25, 2012

Texas Instruments-Advance Information

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