LM4F111E5QR Datasheet, PDF (46/1114 Pages) Texas Instruments – Microcontroller

Architectural Overview
1.3.1.5
1.3.1.6
1.3.2
1.3.2.1
Memory Protection Unit (MPU) (see page 116)
The MPU supports the standard ARM7 Protected Memory System Architecture (PMSA) model. The
MPU provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Floating-Point Unit (FPU) (see page 121)
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate,
and square root operations. It also provides conversions between fixed-point and floating-point data
formats, and floating-point constant instructions.
■ 32-bit instructions for single-precision (C float) data-processing operations
■ Combined Multiply and Accumulate instructions for increased precision (Fused MAC)
■ Hardware support for conversion, addition, subtraction, multiplication with optional accumulate,
division, and square-root
■ Hardware support for denormals and all IEEE rounding modes
■ 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
■ Decoupled three stage pipeline
On-Chip Memory
The LM4F111E5QR microcontroller is integrated with the following set of on-chip memory and
features:
■ 32 KB single-cycle SRAM
■ 128 KB single-cycle Flash memory
■ Internal ROM loaded with StellarisWare software:
– Stellaris Peripheral Driver Library
– Stellaris Boot Loader
– Advanced Encryption Standard (AES) cryptography tables
– Cyclic Redundancy Check (CRC) error detection functionality
■ 2KB EEPROM
SRAM (see page 461)
The LM4F111E5QR microcontroller provides 32 KB of single-cycle on-chip SRAM. The internal
SRAM of the Stellaris devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the Cortex-M4F processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
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April 25, 2012
Texas Instruments-Advance Information