LM4F111E5QR Datasheet, PDF (845/1114 Pages) Texas Instruments – Microcontroller

Stellaris^® LM4F111E5QR Microcontroller
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
UART3 base: 0x4000.F000
UART4 base: 0x4001.0000
UART5 base: 0x4001.1000
UART6 base: 0x4001.2000
UART7 base: 0x4001.3000
Offset 0x03C
Type RO, reset 0x0000.000F
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
LME5RIS LME1RIS LMSBRIS 9BITRIS reserved
Type RO
RO
RO
R/W
RO
Reset
0
0
0
0
0
10
OERIS
RO
0
9
BERIS
RO
0
8
PERIS
RO
0
7
FERIS
RO
0
6
RTRIS
RO
0
5
TXRIS
RO
0
4
RXRIS
RO
0
19
18
17
16
RO
RO
0
0
3
2
reserved
RO
RO
0
0
RO
RO
0
0
1
0
CTSRIS reserved
RO
RO
0
0
Bit/Field
31:16
15
14
13
Name
reserved
LME5RIS
LME1RIS
LMSBRIS
Type
RO
RO
RO
RO
Reset
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Raw Interrupt Status
Value Description
1 The timer value at the 5th falling edge of the LIN Sync Field has
been captured.
0 No interrupt
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR
register.
LIN Mode Edge 1 Raw Interrupt Status
Value Description
1 The timer value at the 1st falling edge of the LIN Sync Field has
been captured.
0 No interrupt
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR
register.
LIN Mode Sync Break Raw Interrupt Status
Value Description
1 A LIN Sync Break has been detected.
0 No interrupt
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR
register.
April 25, 2012
845
Texas Instruments-Advance Information