TI380FPA Datasheet, PDF (9/24 Pages) Texas Instruments – PACKETBLASTER™

TI380FPA
PACKETBLASTERā
SPWS011A − MARCH 1995 − REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
test measurement
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: for a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V, and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V, and the
level at which the signal is said to be high is 2 V, as shown below.
The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically
1.5 ns.
2 V (high)
0.8 V (low)
The test load circuit shown in Figure 2 represents the programmable load of the tester-pin electronics, that are
used to verify timing parameters of TI380FPA output signals.
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
Where:
IOL = 2 mA DC-level verification (all outputs)
IOH = 400 µA (all outputs)
VLOAD = 1.5 V, typical dc-level verification
0.7 V, typical timing verification
CT = 65 pF, typical load-circuit capacitance
Figure 2. Test-Load Circuit
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