TI380FPA Datasheet, PDF (15/24 Pages) Texas Instruments – PACKETBLASTER™

TI380FPA
PACKETBLASTERā
SPWS011A − MARCH 1995 − REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
FPA-bus-master timing: read cycle
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum).
NO.
MIN
MAX
UNIT
32
Access time, address/enable valid on MAX0 and MAX2 to valid data/parity
Access time, address valid on MAXPH, MAXPL, MADH0 −MADH7, and MADL0 −MADL7 to
33
valid data/parity
6tM − 23 ^ns
6tM −23 ^ns
35
Access time, MRAS low to valid data/parity
36
Hold time, valid data/parity after MRAS no longer low
4.5tM −21.5 ns
0
ns
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 −MADH7 and
37†
MADL0 −MADL7 after MRAS high (see Note 11)
2tM −10.5
ns
38
Access time, MCAS low to valid data/parity
39
Hold time, valid data/parity after MCAS no longer low
0
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 −MADH7, and
40†
MADL0 −MADL7 after MCAS high (see Note 11)
2tM −13
3tM −23 ns
ns
ns
41
Delay time, MCAS no longer high to MOE low
Setup time, address/status in the high-impedance state on MAXPH, MAXPL,
42†
MADL0 −MADL7, and MADH0 −MADH7 before MOE no longer high
tM +13 ns
0
ns
43
Access time, MOE low to valid data/parity
44
Pulse duration, MOE low
45
Delay time, MCAS low to MOE no longer low
46
Hold time, valid data/parity in after MOE no longer low
2tM −9
3tM −9
0
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 −MADH7, and
47†
MADL0 −MADL7 after MOE high (see Note 11)
2tM −15
2tM −25 ns
ns
ns
ns
ns
Setup time, address/status in the high-impedance state on MAXPH, MAXPL,
48†
MADL0 −MADL7, and MADH0 −MADH7, before MBEN no longer high
0
ns
49
Access time, MBEN low to valid data/parity
50
Pulse duration, MBEN low
51
Hold time, valid data/parity after MBEN no longer low
2tM −9
0
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0 −MADH7, and
52†
MADL0 −MADL7 after MBEN high (see Note 11)
2tM −15
2tM −25 ns
ns
ns
ns
53
Hold time, MDDIR high after MBEN high, read follows write cycle
1.5tM −12
ns
54
Setup time, MDDIR low before MBEN no longer high
3tM −9
ns
55
Hold time, MDDIR low after MBEN high, write follows read cycle
3tM −12
ns
† _{This specification has been characterized to meet stated value. This parameter is not tested.}
NOTE 11: The data/parity that exists on the address lines will most likely achieve the high-impedance state sometime later than the rising edge
of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read.
The MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address
and does not represent the actual high-impedance state on the address bus.
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