TI380FPA Datasheet, PDF (5/24 Pages) Texas Instruments – PACKETBLASTER™

TI380FPA
PACKETBLASTERā
SPWS011A − MARCH 1995 − REVISED AUGUST 1995
PIN
NAME
NO.
MAXPL
6
MBCLK1
43
MBEN
21
MBGR
37
MBRQ
34
I/O†
I/O
I
O
I
I/O
Pin Functions (Continued)
DESCRIPTION
Local-memory-extended address and parity - low byte. For the first quarter of a memory cycle, MAXPL
carries the extended address bit AX3; for the second quarter of a memory cycle, MAXPL carries
extended address bit AX2; and for the last half of the memory cycle, MAXPL carries the parity bit for
the low-data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX3
AX2
Parity
Parity
Local-bus clock 1. MBCLK1 is referenced for all local-bus transfers.
Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and
MADL buses during the data phase. MBEN is used in conjunction with MDDIR, which selects the buffer
output direction.
H = Buffer output disabled
L = Buffer output enabled
Local bus grant. MBGR indicates that the FPA has been granted access to the adapter local-memory
bus.
Local bus request. MBRQ is used by the FPA to request bus-master access to the adapter
local-memory bus. The FPA also monitors MBRQ to allow it to defer to other higher-priority bus
requests (see Note 1).
Column-address strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle
following the row-address portion of the cycle. MCAS is driven low every memory cycle while the
column address is valid on MADL0 −MADL7, MAXPH, and MAXPL, except when one of the following
conditions occurs:
MCAS
MDDIR
26
O
1) When the address accessed is a TI380C2x or TI380C3x internal register
(>01.0100 − >01.01FF).
2) When the address accessed is in the TI380C2x or TI380C3x external device-address range
(>01.0200 − >01.02FF). This address range includes the FPA registers.
3) When the FPA ROM bit is set, and the address accessed is in adapter ROM-address range
(>00.0000−>00.FFFE or >1F.0000−>1F.FFFE).
Data direction. MDDIR is used as a direction control for bidirectional bus drivers. MDDIR becomes valid
before MBEN becomes active.
31
I/O
H = TI380FPA memory bus write
L = TI380FPA memory bus read
Memory output enable. MOE is used to enable the outputs of the DRAM memory during a read cycle.
MOE is high for EPROM or BIA ROM read cycles.
MOE
1) When the address read is a TI380C2x or TI380C3x internal register (>01.0100−>01.01FF).
2) When the address read is in the TI380C2x or TI380C3x external device-address range
22
O
(>01.0200−>01.02FF). This address range includes the FPA registers.
3) When the FPA ROM bit is set, and the address read is in adapter ROM-address range
(>00.0000−>00.FFFE or 1F.0000−1F.FFFE).
H= Disable DRAM outputs
L = Enable DRAM outputs
MRAS
Row-address strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. MRAS
23
O
is driven low every memory cycle while the row address is valid on MADL0 −MADL7, MAXPH, and
MAXPL for both RAM and register-access cycles.
Memory bus reset. MRESET is the reset signal provided by the TI380C2x or TI380C3x and is used
MRESET
41
I
to reset and initialize the FPA internal logic. While MRESET is asserted, all FPA output pins are in the
high-impedance state.
† _{I = input, O = output}
NOTE 1: Pin has an open-collector output. EXTINT0 should have an individual 1-kΩ pullup resistor. A 4.7-kΩ resistor can lead to transmit
underruns in the adapter system and should not be used. For this reason, a 1-kΩ resistor is specified.
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