TI380FPA Datasheet, PDF (11/24 Pages) Texas Instruments – PACKETBLASTER™

TI380FPA
PACKETBLASTERā
SPWS011A − MARCH 1995 − REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
power up, MBCLK1, MRESET timing
NO.
100† tr(VDD)
Rise time, 1.2 V to minimum VDD-high level
111† td(CKV)
Delay time, minimum VDD-high level to MBCLK1 valid
117† th(VDDH-RSL) Hold time, MRESET low after VDD reaches minimum high level
118† tw(RSH)
Pulse duration, MRESET high
119† tw(RSL)
Pulse duration, MRESET low
† _{This specification is provided as an aid to board design. This specification is not tested.}
100
VDD
Minimun VDD High Level
MIN MAX UNIT
1 ms
3 ms
5
ms
14
µs
14
µs
MBCLK1
111
MRESET
117
118
119
NOTE A: In order to represent the information on one illustration, nonactual phase and timebase characteristics are shown. Refer to specified
parameters for precise information.
Figure 3. Power Up, MBCLK1, and MRESET Timing
clock timing: MBCLK1
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum).
NO.
1 Period of MBCLK1
2 Pulse duration, MBCLK1 high
3 Pulse duration, MBCLK1 low
4 Transition time, MBCLK1
MIN MAX UNIT
83.3
ns
33
ns
33
ns
5
ns
tM
MBCLK1
M8 M1 M2 M3 M4 M5 M6 M7 M8 M1
1
3
2
4
4
Figure 4. Clock Timing: MBCLK1
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