TI380FPA Datasheet, PDF (4/24 Pages) Texas Instruments – PACKETBLASTER™

TI380FPA
PACKETBLASTERā
SPWS011A − MARCH 1995 − REVISED AUGUST 1995
PIN
NAME
NO.
EXTINT0
35
MADH0
8
MADH1
9
MADH2
10
MADH3
13
MADH4
15
MADH5
18
MADH6
19
MADH7
20
MADL0
47
MADL1
48
MADL2
49
MADL3
50
MADL4
52
MADL5
2
MADL6
4
MADL7
5
MAL
32
I/O†
O
I/O
I/O
O
Pin Functions
DESCRIPTION
FPA interrupt request (see Note 1)
Local-memory address, data, and status bus - high byte. For the first quarter of the local-memory cycle,
MADH0 −MADH7 carry address bits AX4 and A0 to A6; for the second quarter, they carry status bits;
and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0, and
the least significant bit is MADH7.
Signal
1Q
AX4,A0−A6
Memory Cycle
2Q
3Q
Status
D0−D7
4Q
D0−D7
Local-memory address, data, and status bus - low byte. For the first quarter of the local-memory cycle,
MADL0 −MADL7 carry address bits A7 to A14; for the second quarter, they carry address bits AX4 and
A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant bit is
MADL0, and the least significant bit is MADL7.
Signal
1Q
A7−A14
Memory Cycle
2Q
3Q
AX4,A0−A6 D8−D15
4Q
D8−D15
Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory
cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,
MAX2, MAXPL, MADH0 −MADH7, and MADL0 −MADL7. Three 8-bit transparent latches can be used
to retain a 20-bit static address throughout the cycle.
Rising edge = No signal latching
Falling edge = Allows the above address signals to be latched
MANT0
MANT1
Test pin inputs. MANT0 and MANT1 should be left unconnected (see Note 2). Module-in-place test
39
38
I
mode is achieved by tying MANT0 and MANT1 to ground. In this mode, all TI380FPA output pins are
in the high-impedance state and internal pullups on all TI380FPA inputs are disabled (except MANT0
and MANT1).
Local-memory-extended address bit. MAX0 drives AX0 at row-address time, which can be located by
MRAS. Normally, MAX0 drives A12 at column address and data time for all cycles.
MAX0
30
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX0
A12
A12
A12
Local-memory-extended address bit. MAX2 drives AX2 at row address time, which can be located by
MRAS. Normally, MAX2 drives A14 at column address and data time for all cycles.
MAX2
MAXPH
28
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX2
A14
A14
A14
Local-memory-extended address and parity - high byte. For the first quarter of a memory cycle, MAXPH
carries the extended address bit AX1; for the second quarter of a memory cycle, MAXPH carries the
extended address bit AX0; and for the last half of the memory cycle, MAXPH carries the parity bit for
7
I/O
the high-data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX1
AX0
Parity
Parity
† _{I = input, O = output}
NOTES: 1. Pin has an open-collector output. EXTINT0 should have an individual 1-kΩ pullup resistor. A 4.7-kΩ resistor can lead to transmit
underruns in the adapter system and should not be used. For this reason, a 1-kΩ resistor is specified.
2. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch or loads). Alternatively, both pins
tied together can be pulled high through a single 4.7-Ω pullup resistor.
4
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