TI380FPA Datasheet, PDF (13/24 Pages) Texas Instruments – PACKETBLASTER™

TI380FPA
PACKETBLASTERā
SPWS011A − MARCH 1995 − REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
FPA-bus-master timing: MRAS, MCAS, and MAL to ADDRESS
t_M is the cycle time of one-eighth of a local-memory cycle (20.83 ns minimum).
NO.
MIN
MAX
15
Setup time, row address on MADL0 −MADL7, MAXPH, and MAXPL before MRAS no longer high 1.5tM − 11.5
16
Hold time, row address on MADL0 −MADL7, MAXPH, and MAXPL after MRAS no longer high
tM −6.5
17
Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle
8tM
18
Pulse duration, MRAS low
4.5tM −9
19
Pulse duration, MRAS high
3.5tM −9
20
Setup time, column address (MADL0 −MADL7, MAXPH, and MAXPL) and status
(MADH0 −MADH7) before MCAS no longer high
0.5tM −9
21
Hold time, column address (MADL0 −MADL7, MAXPH, and MAXPL) and status
(MADH0 −MADH7) after MCAS low
tM −9
22
Hold time, column address (MADL0 −MADL7, MAXPH, and MAXPL) and status
(MADH0 −MADH7) after MRAS no longer high
2.5tM −6.5
23
Pulse duration, MCAS low
3tM −9
24
Pulse duration, MCAS high, refresh cycle follows read or write cycle
2tM −9
25
Hold time, row address on MADL0 −MADL7, MAXPH, and MAXPL after MAL low
1.5tM −9
26
Setup time, row address on MADL0 −MADL7, MAXPH, and MAXPL before MAL no longer high
tM −9
27
Pulse duration, MAL high
tM −9
28
Setup time, address/enable on MAX0 and MAX2 before MAL no longer high
tM −9
29
Hold time, address/enable of MAX0 and MAX2 after MAL low
1.5tM −9
30
Setup time, address on MADH0 −MADH7 before MAL no longer high
tM −9
31
Hold time, address on MADH0 −MADH7 after MAL low
1.5tM −9
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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