DS100BR111A_14 Datasheet, PDF (9/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
www.ti.com
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Parameter
Test Conditions
Min
SERIAL BUS INTERFACE DC SPECIFICATIONS: ⁽¹⁾
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Capacitance for SDA and SCL
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
See ⁽²⁾
See ^{(2) (3) (4)}
Pullup V_DD = 3.3V, ^{(2) (3) (5)}
Pullup V_DD = 2.5V, ^{(2) (3) (5)}
2.375
-200
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
(6)
280
TBUF
Bus Free Time Between Stop and
Start Condition
1.3
THD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
0.6
clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
0.6
TSU:STO
Stop Condition Setup Time
0.6
THD:DAT
Data Hold Time
0
TSU:DAT
Data Setup Time
100
T_LOW
Clock Low Period
1.3
T_HIGH
Clock High Period
See ⁽¹⁾
0.6
t_F
Clock/Data Fall Time
See ⁽¹⁾
t_R
Clock/Data Rise Time
See ⁽¹⁾
t_POR
Time in which a device must be
See ^{(1) (4)}
operational after power-on reset
Typ
2000
1000
400
Max
0.8
3.6
3.6
+200
10
400
520
50
300
300
500
Units
V
V
mA
V
µA
pF
Ω
Ω
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ms
(1) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(2) Recommended value.
(3) Recommended maximum capacitance load per bus segment is 400pF.
(4) Ensured by Design. Parameter not tested in production.
(5) Maximum termination voltage should be identical to the device supply voltage.
(6) EEPROM interface requires 400 KHz capable EEPROM device.
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