DS100BR111A_14 Datasheet, PDF (12/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
www.ti.com
NOTE
Settings are approximate and will change based on PCB material, trace dimensions, and
driver waveform characteristics.
Level
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VOD_SEL
0
0
0
0
Float
Float
Float
Float
R
R
R
R
1
1
1
1
Table 3. De-emphasis and Output Voltage Settings
DEMA/B
0
Float
R
1
0
Float
R
1
0
Float
R
1
0
Float
R
1
SMBus Register DEM Level
000
010
011
101
000
010
011
101
000
010
011
101
000
001
001
010
SMBus Register VOD Level
000
000
000
000
011
011
011
011
101
101
101
101
100
100
110
110
NOTE
Below 850mV output setting De-emphasis gain is reduced.
VOD (mV)
575
575
575
575
850
850
850
850
1050
1050
1050
1050
950
950
1150
1150
DEM (dB)
0
- 3.5
-6
-9
0
- 3.5
-6
-9
-0
- 3.5
-6
-9
0
- 1.5
- 1.5
- 3.5
NOTE
The DS100BR111A VOD for OUTPUT A is limited to 575 mV in pin mode (ENSMB=0).
With ENSMB = 1 or FLOAT, the VOD for OUTPUT A can be adjusted with SMBus register
0x23 [4:2] as shown in Table 8.
NOTE
In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the
DS100BR111A AD0-AD3 pins are internally forced to 0'h
Table 4. Signal Detect Threshold Level⁽¹⁾
SD_TH
0
20K to GND
Float (Default)
1
SMBus REG bit [3:2] and [1:0]
10
01
00
11
Assert Level (Typical)
210 mV
160 mV
180 mV
190 mV
(1) VDD = 2.5V, 25°C, and 010101 pattern at 10 Gbps
De-assert Level (Typical)
150 mV
100 mV
110 mV
130 mV
12
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