DS100BR111A_14 Datasheet, PDF (13/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

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DS100BR111A
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
APPLICATIONS INFORMATION
4-Level Input Configuration Guidelines
The 4-level input pins utilize a resistor divider to help set the 4 valid levels. There is an internal 30K pull-up and a
60K pull-down connected to the package pin. These resistors, together with the external resistor connection
combine to achieve the desired voltage level. Using the 1K pull-up, 1K pull-down, no connect, and 20K pull-down
provide the optimal voltage levels for each of the four input states.
Table 5. 4-Level Input Voltage
Level
Setting
3.3V Mode
2.5V Mode
0
01K to GND
0.1 V
0.08 V
R
20K to GND
F
FLOAT
1
1K to V_DD/V_IN
• Typical 4-Level Input Thresholds
0.33 * V_IN
0.67 * V_IN
V_IN - 0.05V
0.33 * V_DD
0.67 * V_DD
V_IN - 0.04V
– Level 1 - 2 = 0.2 V_IN or V_DD
– Level 2 - 3 = 0.5 V_IN or V_DD
– Level 3 - 4 = 0.8 V_IN or V_DD
In order to minimize the startup current associated with the integrated 2.5V regulator the 1K pull-up / pull-down
resistors are recommended. If several 4 level inputs require the same setting, it is possible to combine two or
more 1K resistors into a single lower value resistor. As an example; combining two inputs with a single 500Ω
resistor is a good way to save board space.
PCB Layout Guidelines
The CML inputs and outputs have been optimized to work with interconnects using a controlled differential
impedance of 85 - 100Ω. It is preferable to route differential lines exclusively on one layer of the board,
particularly for the input traces. The use of vias should be avoided if possible. If vias must be used, they should
be used sparingly and must be placed symmetrically for each side of a given differential pair. Whenever
differential vias are used the layout must also provide for a low inductance path for the return currents as well.
Route the differential signals away from other signals and noise sources on the printed circuit board. See
SNOA401Q AN-1187 for additional information on WQFN packages.
Different transmission line topologies can be used in various combinations to achieve the optimal system
performance. Impedance discontinuities at vias can be minimized or eliminated by increasing the swell around
each hole and providing for a low inductance return current path. When the via structure is associated with thick
backplane PCB, further optimization such as back drilling is often used to reduce the detrimental high frequency
effects of stubs on the signal path.
Power Supply Configuration Guidelines
The DS100BR111A can be configured for 2.5V operation or 3.3V operation. The lists below outline required
connections for each supply selection.
3.3V Mode of Operation
1. Tie VDD_SEL = 0 with 1K resistor to GND.
2. Feed 3.3V supply into VIN pin. Local 1.0 uF decoupling at VIN is recommended.
3. See information on VDD bypass below.
4. SDA and SCL pins should connect pull-up resistor to VIN
5. Any 4-Level input which requires a connection to "Logic 1" should use a 1K resistor to VIN
2.5V Mode of Operation
6. VDD_SEL = Float
7. VIN = Float
8. Feed 2.5V supply into VDD pins.
Copyright © 2012–2013, Texas Instruments Incorporated
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