DS100BR111A_14 Datasheet, PDF (25/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
www.ti.com
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
Table 8. SMBus Register Map (continued)
Address
Register
Name
0x04
Control 3
0x05
0x06
CRC 1
CRC 2
Bits
Field
7:6 eSATA Mode
Enable
5
TX_DIS Override
Enable
4
TX_DIS Value
Channel A
3
TX_DIS Value
Channel B
2
Reserved
1:0 Reserved
7:0 CRC[7:0]
7
Disable EEPROM
CFG
6:5 Reserved
4
Reserved
3
CRC Slave Mode
Enable
0x07
2:1
0
Digital Reset 7
and Control ₆
Reserved
CRC Enable
Reserved
Reset Regs
0x08
5
4:0
Pin Override 7
6
Reset SMBus
Master
Reserved
Reserved
Override Idle
Threshold
5
Reserved
4
Override IDLE
0x0C
0x0D
CH A
Analog
Override 1
CH A
Reserved
3
Reserved
2
Reserved
1
Override DEM
0
Reserved
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3:0 Reserved
7:0 Reserved
Type Default
R/W 0x00
EEPROM
Reg Bit
Yes
Description
[7] Channel A (1)
[6] Channel B (1)
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
1: TX Disabled
0: TX Enabled
R/W 0x00
R/W 0x10
R/W 0x01
R/W 0x00
R/W 0x00
R/W 0x00
Set bit to 0'b
Set bits to 00'b
Slave Mode CRC Bits
Disable Master Mode EEPROM Configuration
Set bits to 00'b
Yes
Set bit to 1'b
[1]: CRC Disable (No CRC Check)
[0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED register
updates will NOT take effect until correct CRC
value is loaded
Set bits to 00'b
Slave CRC Trigger
Set bit to 0'b
Self clearing reset for registers
Writing a [1] will return register settings to default
values.
Self clearing reset for SMBus master state
machine
Set bits to 0001'b
Set bit to 0
Yes
[1]: Override by Channel - see Reg 0x13 and
0x19
[0]: SD_TH pin control
Yes
Set bit to 0'b
Yes
[1]: Force IDLE by Channel - see Reg 0x0E and
0x15
[0]: Normal Operation
Yes
Set bit to 0'b
Yes
Set bit to 0'b
Yes
Yes
Set bit to 0'b
Set bit to 0'b
Set bit to 0'b
Set bit to 0'b
Set bit to 0'b
Set bits to 000'b
Set bits to 00'h
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