DS100BR111A_14 Datasheet, PDF (3/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
www.ti.com
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
Pin Name
Pin Number
Differential High Speed I/O's
INA+, INA- ,
INB+, INB-,
24, 23
11, 12
OUTA+, OUTA-,
OUTB+, OUTB-,
7, 8
20, 19
Control Pins
ENSMB
3
ENSMB = 1 (SMBUS MODE)
SCL
5
SDA
4
AD0-AD3
10, 9, 2, 1
PIN DESCRIPTIONS⁽¹⁾⁽²⁾
I/O, Type
Pin Description
I, CML
O,CML
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
termination resistor connects INx+ to VDD and INx- to VDD when enabled.
Inverting and non-inverting 50Ω driver outputs with de-emphasis. Compatible with
AC coupled CML inputs.
I, LVCMOS
Float
System Management Bus (SMBus) enable pin
Tie HIGH = Register Access, SMBus Slave mode
FLOAT = SMBus Master read from External EEPROM
Tie LOW = External Pin Control Mode
I, LVCMOS
O, Open
Drain
I, LVCMOS,
O, Open
Drain
I, LVCMOS,
Float
(4-Levels)
ENSMB Master or Slave mode
SMBUS clock input pin is enabled. A clock input in Slave mode. Can also be a
clock output in Master mode.
ENSMB Master or Slave mode
The SMBus bidirectional SDA pin is enabled. Data input or open drain (pull-down
only) output.
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus
slave address inputs. There are 16 addresses supported by these pins.
Pins must be tied LOW or HIGH when used to define the device SMBus address.
(3)
READEN#
17
DONE#
18
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
DEMA, DEMB
4, 5
TX_DIS
6
VOD_SEL
17
VDD_SEL
16
MODE
18
I, LVCMOS When using an External EEPROM, a transition from high to low starts the load
from the external EEPROM
IO, LVCMOS, EEPROM Download Status
Float
HIGH indicates Error / Still Loading
(4-Levels) LOW indicates download complete. No Error.
I, LVCMOS,
Float
(4-Levels)
EQA/B, 0/1 control the level of equalization of each channel. The EQA/B pins are
active only when ENSMB is de-asserted (LOW).
When ENSMB goes high the SMBus registers provide independent control of each
lane, and the EQB0/B1 pins are converted to SMBUS AD2/AD3 inputs. Table 2
IO, LVCMOS, DEMA/B controls the level of de-emphasis. The DEMA/B pins are only active when
Float
ENSMB is de-asserted (LOW). Each of the 4 A/B channels have the same level
(4-Levels) unless controlled by the SMBus control registers. When ENSMB goes high the
SMBus registers provide independent control of each lane and the DEM pins are
converted to SMBUS SCL and SDA pins.
Table 3
I, LVCMOS
DS100BR111A
High = OUTA Enabled /OUTB Disabled
Low = OUTA/B Enabled
I, LVCMOS,
Float
(4-Levels)
VOD select.
High = (VOD = 950 mV / 1150 mV)
Float = (VOD = 850 mV)
20K = (VOD = 1050 mV)
Low = (VOD = 575 mV)
(4)_{See Table 4 for additional information.}(3)
I, Internal
Pull-up
Enables the 3.3V to 2.5V internal regulator
Low = 3.3 V Operation
Float = 2.5 V Operation
I, LVCMOS,
Float
(4-Levels)
Controls Device Mode of Operation
High = Continuous Talk (no output IDLE)
Float = Slow OOB
20KΩ = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of inactivity. SD
stays active.
Low = SAS Mode, Fast OOB
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured. Unless the
"Float" level is desired; 4-Level input pins require a minimum 1K resistor to GND, VDD (in 2.5V mode), or VIN (in 3.3V mode).
(2) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
(3) Setting VOD_SEL = High in SMBus Mode will force the SMBus Address = B0'h
(4) DS100BR111A OUTA is limited to 575mV in pin mode
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