DS100BR111A_14 Datasheet, PDF (10/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
TIMING DIAGRAMS
Figure 2. CML Output Transition Times
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Figure 3. Propagation Delay Timing Diagram
Figure 4. Idle Timing Diagram
t_LOW
t_R
t_HIGH
t_BUF
t_HD:STA
t_HD:DAT
t_F
t_SU:STA
t_SU:DAT
t_SU:STO
SP
ST
ST
SP
Figure 5. SMBus Timing Parameters
SCL
SDA
10
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