DS100BR111A_14 Datasheet, PDF (2/39 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS100BR111A
SNLS400C – JANUARY 2012 – REVISED APRIL 2013
Typical Application
ASIC/FPGA
DS100BR111A
Interconnect
Cable
DS100BR111A
ASIC/FPGA
Block Diagram - Detail View Of Channel (1 Of 2)
VDD
VOD
VOD/ DE-EMPHASIS CONTROL
SMBus
DEM
50:
IN+
50:
EQ
SMBus
OUTBUF
OUT+
IN-
OUT-
Tx IDLE Enable
EQ[1:0]
SMBus
IDLE DETECT
Channel
Status
and
Control
LOS
SD_TH
TX_DIS
MODE
Pin Diagram
OUTA+ 7
OUTA- 8
AD1/EQA1 9
AD0/EQA0 10
INB+ 11
INB- 12
SMBUS AND
CONTROL
24 INA+
23 INA-
22 _VDD
21 _VDD
20 OUTB+
19 OUTB-
www.ti.com
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Figure 1. DS100BR111A Pin Diagram 24 lead
2
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS100BR111A