AM1802_16 Datasheet, PDF (89/182 Pages) Texas Instruments – AM1802 ARM® Microprocessor

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AM1802
SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014
DDR2/mDDR Memory Controller
DDR_D[0:7]
DDR_DQM[0]
DDR_DQS[0]
ODT
T
DQ0 - DQ7
BA0-BA2
A0-A13
T
DM
T
DQS
NC
DQS
DDR_BA[0:2]
T
DDR_A[0:13]
T
DDR_CLKP
T
DDR_CLKN
T
DDR_CS
T
DDR_CAS
T
DDR_RAS
T
DDR_WE
T
DDR_CKE
T
DDR_DQM1
DDR_DQS1
DDR_D[8:15]
DDR_ZP
DDR_DQGATE0
DDR_DQGATE1
(1)
T
T
DDR_VREF
0.1 μF⁽²⁾
T
T
NC
T
0.1 μF⁽²⁾
0.1 μF⁽²⁾
CK
CK
CS
CAS
RAS
WE
CKE
VREF
BA0-BA2
A0-A13
CK
CK
CS
CAS
RAS
WE
CKE
DM
DQS
DQS
DQ0 - DQ7
ODT
VREF⁽³⁾
DDR_DVDD18
0.1 μF
0.1 μF
1 K Ω 1%
VREF
1 K Ω 1%
T Terminator, if desired. See terminator comments.
(1) See Figure 6-23 for DQGATE routing specifications.
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,
these capacitors can be eliminated completely.
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.
Figure 6-17. DDR2/mDDR Dual-Memory High Level Schematic
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Peripheral Information and Electrical Specifications
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