AM1802_16 Datasheet, PDF (27/182 Pages) Texas Instruments – AM1802 ARM® Microprocessor

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AM1802
SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014
3.7.12 Multichannel Audio Serial Ports (McASP)
Table 3-14. Multichannel Audio Serial Ports Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
PULL ⁽²⁾
POWER
GROUP ⁽³⁾
DESCRIPTION
McASP0
AXR15 / GP0[7]
A4
I/O
CP[1]
A
AXR14 / GP0[6]
B4
I/O
CP[2]
A
AXR13 / GP0[5]
B3
I/O
CP[2]
A
AXR12 / GP0[4]
C4
I/O
CP[2]
A
AXR11 / GP0[3]
C5
I/O
CP[2]
A
AXR10 / GP0[2]
D4
I/O
CP[2]
A
AXR9 / GP0[1]
C3
I/O
CP[2]
A
AXR8 / GP0[0]
AXR7 / GP1[15]
E4
I/O
D2
I/O
CP[3]
CP[4]
A
McASP0 serial data
A
AXR6 / GP1[14] / MII_TXEN
C1
I/O
CP[5]
A
AXR5 / GP1[13] / MII_TXCLK
D3
I/O
CP[5]
A
AXR4 / GP1[12] / MII_COL
D1
I/O
CP[5]
A
AXR3 / GP1[11] / MII_TXD[3]
E3
I/O
CP[5]
A
AXR2 / GP1[10] / MII_TXD[2]
E2
I/O
CP[5]
A
AXR1 / GP1[9] / MII_TXD[1]
E1
I/O
CP[5]
A
AXR0 / GP8[7] / MII_TXD[0]
F3
I/O
CP[6]
A
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10]
A3
I/O
CP[0]
A
McASP0 transmit master clock
ACLKX / GP0[14]
B1
I/O
CP[0]
A
McASP0 transmit bit clock
AFSX / GP0[12]
B2
I/O
CP[0]
A
McASP0 transmit frame sync
AHCLKR / UART1_RTS /GP0[11]
A2
I/O
CP[0]
A
McASP0 receive master clock
ACLKR / GP0[15]
A1
I/O
CP[0]
A
McASP0 receive bit clock
AFSR / GP0[13]
C2
I/O
CP[0]
A
McASP0 receive frame sync
AMUTE / UART2_RTS / GP0[9]
D5
I/O
CP[0]
A
McASP0 mute output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown
circuits, see the Device Operating Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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