AM1802_16 Datasheet, PDF (19/182 Pages) Texas Instruments – AM1802 ARM® Microprocessor

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AM1802
SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014
Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
EMA_A[22] / MMCSD0_CMD / GP4[6]
EMA_A[21] / MMCSD0_DAT[0] / GP4[5]
EMA_A[20] / MMCSD0_DAT[1] / GP4[4]
EMA_A[19] / MMCSD0_DAT[2] /GP4[3]
EMA_A[18] / MMCSD0_DAT[3] / GP4[2]
EMA_A[17] / MMCSD0_DAT[4] /GP4[1]
EMA_A[16] / MMCSD0_DAT[5] / GP4[0]
EMA_A[15] / MMCSD0_DAT[6] / GP5[15]
EMA_A[14] / MMCSD0_DAT[7] / GP5[14]
EMA_A[13] / GP5[13]
EMA_A[12] / GP5[12]
EMA_A[11] / GP5[11]
EMA_A[10] / GP5[10]
EMA_A[9] / GP5[9]
EMA_A[8] / GP5[8]
EMA_A[7] / GP5[7]
EMA_A[6] / GP5[6]
EMA_A[5] / GP5[5]
EMA_A[4] / GP5[4]
EMA_A[3] / GP5[3]
EMA_A[2] / GP5[2]
EMA_A[1] / GP5[1]
EMA_A[0] / GP5[0]
EMA_BA[0] / GP2[8]
EMA_BA[1] / GP2[9]
EMA_CLK / GP2[7]
EMA_SDCKE / GP2[6]
EMA_RAS / GP2[5]
EMA_CAS / GP2[4]
EMA_CS[0] / GP2[0]
EMA_CS[2] / GP3[15]
EMA_CS[3] / GP3[14]
EMA_CS[4] / GP3[13]
EMA_CS[5] / GP3[12]
EMA_A_RW / GP3[9]
EMA_WE / GP3[11]
EMA_WEN_DQM[1] / GP2[2]
EMA_WEN_DQM[0] / GP2[3]
EMA_OE / GP3[10]
EMA_WAIT[0] / GP3[8]
EMA_WAIT[1] / GP2[1]
TYPE ⁽¹⁾
NO.
A10
O
B10
O
A11
O
C10
O
E11
O
B11
O
E12
O
C11
O
A12
O
D11
O
D13
O
B12
O
C12
O
D12
O
A13
O
B13
O
E13
O
C13
O
A14
O
D14
O
B14
O
D15
O
C14
O
C15
O
A15
O
B7
O
D8
O
A16
O
A9
O
A18
O
B17
O
A17
O
F9
O
B16
O
D10
O
B9
O
A5
O
C8
O
B15
O
B18
I
B19
I
PULL ⁽²⁾
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[18]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[19]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[20]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
CP[16]
POWER
GROUP ⁽³⁾
DESCRIPTION
B
B
B
B
B
B
B
B
B
B
B
B
EMIFA address bus
B
B
B
B
B
B
B
B
B
B
B
B
EMIFA bank address
B
B
EMIFA clock
B
EMIFA SDRAM clock enable
B
EMIFA SDRAM row address strobe
B
EMIFA SDRAM column address strobe
B
EMIFA SDRAM Chip Select
B
B
EMIFA Async Chip Select
B
B
B
EMIFA Async Read/Write control
B
EMIFA SDRAM write enable
B
EMIFA write enable/data mask for
EMA_D[15:8]
B
EMIFA write enable/data mask for EMA_D[7:0]
B
EMIFA output enable
B
EMIFA wait input/interrupt
B
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