LM3S1H11 Datasheet, PDF (868/956 Pages) Texas Instruments – Stellaris® LM3S1H11 Microcontroller

Signal Tables
Table 19-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
VDDC
C3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 21-6 on page 900.
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
PD5
I/O
TTL
GPIO port D bit 5.
AIN6
I
Analog Analog-to-digital converter input 6.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
C6
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 21-2 on page 895, regardless of system
implementation.
PH1
I/O
TTL
GPIO port H bit 1.
C8
CCP7
I/O
TTL
Capture/Compare/PWM 7.
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PH0
I/O
TTL
GPIO port H bit 0.
C9
CCP6
I/O
TTL
Capture/Compare/PWM 6.
EPI0S6
I/O
TTL
EPI module 0 signal 6.
PG7
I/O
TTL
GPIO port G bit 7.
C10
CCP5
I/O
TTL
Capture/Compare/PWM 5.
EPI0S31
I/O
TTL
EPI module 0 signal 31.
C11
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C12
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
D3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 21-6 on page 900.
PH3
D10
EPI0S0
I/O
TTL
GPIO port H bit 3.
I/O
TTL
EPI module 0 signal 0.
PH2
I/O
TTL
GPIO port H bit 2.
D11
C1o
O
TTL
Analog comparator 1 output.
EPI0S1
I/O
TTL
EPI module 0 signal 1.
868
January 23, 2012
Texas Instruments-Production Data