LM3S1H11 Datasheet, PDF (291/956 Pages) Texas Instruments – Stellaris® LM3S1H11 Microcontroller

Stellaris^® LM3S1H11 Microcontroller
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EXTW LOWBAT RTCALT1 RTCALT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C R/W1C R/W1C R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
0
Name
reserved
EXTW
LOWBAT
RTCALT1
RTCALT0
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
0
External Wake-Up Masked Interrupt Clear
Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
R/W1C
0
Low Battery Voltage Masked Interrupt Clear
Writing a 1 to this bit clears the LOWBAT bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
R/W1C
0
RTC Alert1 Masked Interrupt Clear
Writing a 1 to this bit clears the RTCALT1 bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
R/W1C
0
RTC Alert0 Masked Interrupt Clear
Writing a 1 to this bit clears the RTCALT0 bit in the HIBRIS and HIBMIS
registers.
Reads return an indeterminate value.
January 23, 2012
291
Texas Instruments-Production Data