LM3S1H11 Datasheet, PDF (25/956 Pages) Texas Instruments – Stellaris® LM3S1H11 Microcontroller

Stellaris^® LM3S1H11 Microcontroller
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 663
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 663
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 664
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 664
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 666
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 667
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 668
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 669
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 670
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 675
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 675
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 675
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 675
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 675
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 675
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 675
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 675
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 677
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 677
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 677
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 677
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 677
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 677
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 677
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 677
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 679
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 694
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 696
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 699
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 702
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 703
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 704
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 705
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 707
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 711
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 713
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 717
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 721
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 725
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 727
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 728
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 729
Register 17: UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 730
Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 731
Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 732
Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 733
Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 734
Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 735
January 23, 2012
25
Texas Instruments-Production Data