LM3S1H11 Datasheet, PDF (519/956 Pages) Texas Instruments – Stellaris® LM3S1H11 Microcontroller

Stellaris^® LM3S1H11 Microcontroller
Bit/Field
7
6
5
4
3:1
0
Name
XFEMPTY
INITSEQ
WBUSY
NBRBUSY
reserved
ACTIVE
Type
RO
RO
RO
RO
RO
RO
Reset
0
Description
External FIFO Empty
This bit provides information on the XFIFO when in the FIFO sub-mode
of the Host Bus n mode with the XFEEN bit set in the EPIHBnCFG
register. The EPI0S27 signal reflects the status of this bit.
Value Description
0 The external device is not gating the clock.
1 The XFIFO is signaling as empty (the FIFO empty signal is
high).
Attempts to read in this case are stalled until the XFIFO empty
signal goes low or the counter times out as specified by the
MAXWAIT field.
0
Initialization Sequence
Value Description
0 The SDRAM interface is not in the wakeup period.
1 The SDRAM interface is running through the wakeup period
(greater than 100 μs).
If an attempt is made to read or write the SDRAM during this
period, the access is held off until the wakeup period is
complete.
0
Write Busy
Value Description
0 The external interface is not performing a write.
1 The external interface is performing a write.
0
Non-Blocking Read Busy
Value Description
0 The external interface is not performing a non-blocking read.
1 The external interface is performing a non-blocking read, or if
the non-blocking read is paused due to a write.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Register Active
Value Description
0 If NBRBUSY is set, the EPIRPSTD0 register is active.
If the NBRBUSY bit is clear, then neither EPIRPSTDx register is
active.
1 The EPIRPSTD1 register is active.
January 23, 2012
519
Texas Instruments-Production Data