LM3S1H11 Datasheet, PDF (10/956 Pages) Texas Instruments – Stellaris® LM3S1H11 Microcontroller

Table of Contents
List of Figures
Figure 1-1. Stellaris LM3S1H11 Microcontroller High-Level Block Diagram ............................... 35
Figure 2-1. CPU Block Diagram ............................................................................................. 55
Figure 2-2. TPIU Block Diagram ............................................................................................ 56
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 58
Figure 2-4. Bit-Band Mapping ................................................................................................ 78
Figure 2-5. Data Storage ....................................................................................................... 79
Figure 2-6. Vector Table ........................................................................................................ 85
Figure 2-7. Exception Stack Frame ........................................................................................ 87
Figure 3-1. SRD Use Example ............................................................................................. 101
Figure 4-1. JTAG Module Block Diagram .............................................................................. 162
Figure 4-2. Test Access Port State Machine ......................................................................... 165
Figure 4-3. IDCODE Register Format ................................................................................... 171
Figure 4-4. BYPASS Register Format ................................................................................... 171
Figure 4-5. Boundary Scan Register Format ......................................................................... 172
Figure 5-1. Basic RST Configuration .................................................................................... 176
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 176
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 177
Figure 5-4. Power Architecture ............................................................................................ 180
Figure 5-5. Main Clock Tree ................................................................................................ 183
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 268
Figure 6-2. Using a Crystal as the Hibernation Clock Source ................................................. 271
Figure 6-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 271
Figure 7-1. Internal Memory Block Diagram .......................................................................... 294
Figure 8-1. μDMA Block Diagram ......................................................................................... 341
Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 347
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 349
Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 350
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 352
Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 353
Figure 9-1. Digital I/O Pads ................................................................................................. 405
Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 406
Figure 9-3. GPIODATA Write Example ................................................................................. 407
Figure 9-4. GPIODATA Read Example ................................................................................. 407
Figure 10-1. EPI Block Diagram ............................................................................................. 458
Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 466
Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 466
Figure 10-4. SDRAM Write Cycle ........................................................................................... 467
Figure 10-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 473
Figure 10-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 475
Figure 10-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 476
Figure 10-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 0, RDHIGH = 0 ............................................................................................... 476
Figure 10-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual
CSn .................................................................................................................. 477
Figure 10-10. Continuous Read Mode Accesses ...................................................................... 477
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January 23, 2012
Texas Instruments-Production Data