TM4C129ENCZAD Datasheet, PDF (859/2037 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCZAD Microcontroller
Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1n^a
Address
Data
a _{BSEL0n and BSEL1n are available in Host-Bus 16 mode only.}
Data
Figure 11-14 on page 860 shows a write cycle with the address and data signals multiplexed (MODE
field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being
asserted along with CSn and data being latched on the rising edge of RDn.
June 18, 2014
859
Texas Instruments-Production Data