TM4C129ENCZAD Datasheet, PDF (29/2037 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCZAD Microcontroller
Register 80: Analog-to-Digital Converter Software Reset (SRADC), offset 0x538 .................................. 380
Register 81: Analog Comparator Software Reset (SRACMP), offset 0x53C .......................................... 381
Register 82: Pulse Width Modulator Software Reset (SRPWM), offset 0x540 ....................................... 382
Register 83: Quadrature Encoder Interface Software Reset (SRQEI), offset 0x544 ............................... 383
Register 84: EEPROM Software Reset (SREEPROM), offset 0x558 .................................................... 384
Register 85: CRC and Cryptographic Modules Software Reset (SRCCM), offset 0x574 ......................... 385
Register 86: Ethernet MAC Software Reset (SREMAC), offset 0x59C .................................................. 386
Register 87: Watchdog Timer Run Mode Clock Gating Control (RCGCWD), offset 0x600 ...................... 387
Register 88: 16/32-Bit General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER), offset
0x604 ........................................................................................................................... 388
Register 89: General-Purpose Input/Output Run Mode Clock Gating Control (RCGCGPIO), offset
0x608 ........................................................................................................................... 390
Register 90: Micro Direct Memory Access Run Mode Clock Gating Control (RCGCDMA), offset
0x60C ........................................................................................................................... 393
Register 91: EPI Run Mode Clock Gating Control (RCGCEPI), offset 0x610 ......................................... 394
Register 92: Hibernation Run Mode Clock Gating Control (RCGCHIB), offset 0x614 ............................. 395
Register 93: Universal Asynchronous Receiver/Transmitter Run Mode Clock Gating Control (RCGCUART),
offset 0x618 .................................................................................................................. 396
Register 94: Synchronous Serial Interface Run Mode Clock Gating Control (RCGCSSI), offset
0x61C ........................................................................................................................... 398
Register 95: Inter-Integrated Circuit Run Mode Clock Gating Control (RCGCI2C), offset 0x620 ............. 399
Register 96: Universal Serial Bus Run Mode Clock Gating Control (RCGCUSB), offset 0x628 ............... 401
Register 97: Ethernet PHY Run Mode Clock Gating Control (RCGCEPHY), offset 0x630 ...................... 402
Register 98: Controller Area Network Run Mode Clock Gating Control (RCGCCAN), offset 0x634 ......... 403
Register 99: Analog-to-Digital Converter Run Mode Clock Gating Control (RCGCADC), offset 0x638 .... 404
Register 100: Analog Comparator Run Mode Clock Gating Control (RCGCACMP), offset 0x63C ............. 405
Register 101: Pulse Width Modulator Run Mode Clock Gating Control (RCGCPWM), offset 0x640 .......... 406
Register 102: Quadrature Encoder Interface Run Mode Clock Gating Control (RCGCQEI), offset
0x644 ........................................................................................................................... 407
Register 103: EEPROM Run Mode Clock Gating Control (RCGCEEPROM), offset 0x658 ....................... 408
Register 104: CRC and Cryptographic Modules Run Mode Clock Gating Control (RCGCCCM), offset
0x674 ........................................................................................................................... 409
Register 105: Ethernet MAC Run Mode Clock Gating Control (RCGCEMAC), offset 0x69C ..................... 410
Register 106: Watchdog Timer Sleep Mode Clock Gating Control (SCGCWD), offset 0x700 .................... 411
Register 107: 16/32-Bit General-Purpose Timer Sleep Mode Clock Gating Control (SCGCTIMER), offset
0x704 ........................................................................................................................... 412
Register 108: General-Purpose Input/Output Sleep Mode Clock Gating Control (SCGCGPIO), offset
0x708 ........................................................................................................................... 414
Register 109: Micro Direct Memory Access Sleep Mode Clock Gating Control (SCGCDMA), offset
0x70C ........................................................................................................................... 417
Register 110: EPI Sleep Mode Clock Gating Control (SCGCEPI), offset 0x710 ....................................... 418
Register 111: Hibernation Sleep Mode Clock Gating Control (SCGCHIB), offset 0x714 ........................... 419
Register 112: Universal Asynchronous Receiver/Transmitter Sleep Mode Clock Gating Control
(SCGCUART), offset 0x718 ............................................................................................ 420
Register 113: Synchronous Serial Interface Sleep Mode Clock Gating Control (SCGCSSI), offset
0x71C ........................................................................................................................... 422
Register 114: Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C), offset 0x720 ........... 423
Register 115: Universal Serial Bus Sleep Mode Clock Gating Control (SCGCUSB), offset 0x728 ............. 425
Register 116: Ethernet PHY Sleep Mode Clock Gating Control (SCGCEPHY), offset 0x730 .................... 426
June 18, 2014
29
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