TM4C129ENCZAD Datasheet, PDF (1022/2037 Pages) Texas Instruments – Tiva Microcontroller

Data Encryption Standard Accelerator (DES)
14.2
The first option provides highest level of security; the last option is compatible with single DES. See
Table 14-1 on page 1022 for key use.
Table 14-1. Key Repartition
Mode
64-bit (DES)
192-bit (3DES)
Key1_L
√
√
Key1_H
√
√
Key2_L
X
√
Key2_H
X
√
Key3_L
X
√
Key3_H
X
√
ECB, CBC, and CFB modes can be used with DES and 3DES modes.
DES Block Diagram
The module architecture consists of primary blocks, as shown in Figure 14-1 on page 1022. The DES
module includes a register interface, and a µDMA and interrupt interface.
Depending of the availability of context and data, the DES engine is automatically triggered to
process the data. The DES engine is directly connected to the context and data registers such that
it can immediately start processing when all data is available.
Packets (blocks of 64 bits) must be parsed into blocks and sequentially fed into the DES, which can
buffer the block currently being processed as well as an additional block that may be queued in
advance.
Figure 14-1. DES Block Diagram
I/O Control FSM/ DMA Requests
Mode
Control
FSM
DES
Feedback
Mode
cotnrol
DES Cipher Core
Context
Registers
14.2.1
µDMA Control
The µDMA and interrupt request logic is controlled by the DES Engine. The DES Engine can have
multiple µDMA request signals active in parallel.
There are three DMA channels available:
1022
Texas Instruments-Production Data
June 18, 2014