TM4C129ENCZAD Datasheet, PDF (1115/2037 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCZAD Microcontroller
Bit/Field
8
7
6
5
Name
TBILD
TBSNAPS
TBWOT
TBMIE
Type
RW
RW
RW
RW
Reset
0
0
Description
GPTM Timer B Interval Load Write
Value Description
0 Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next cycle. Also update the
GPTMTBPS register with the value in the GPTMTBPR register
on the next cycle.
1 Update the GPTMTBR and GPTMTBV registers with the value
in the GPTMTBILR register on the next timeout. Also update
the GPTMTBPS register with the value in the GPTMTBPR
register on the next timeout.
Note the state of this bit has no effect when counting up.
The bit descriptions above apply if the timer is enabled and running. If
the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR,
GPTMTBV and are updated when the timer is enabled. If the timer is
stalled (TBSTALL is set), GPTMTBR and GPTMTBPS are updated
according to the configuration of this bit.
GPTM Timer B Snap-Shot Mode
Value Description
0 Snap-shot mode is disabled.
1 If Timer B is configured in the periodic mode, the actual
free-running value of Timer B is loaded at the time-out event
into the GPTM Timer B (GPTMTBR) register. If the timer
prescaler is used, the prescaler snapshot is loaded into the
GPTM Timer B (GPTMTBPR).
0
GPTM Timer B Wait-on-Trigger
Value Description
0 Timer B begins counting as soon as it is enabled.
1 If Timer B is enabled (TBEN is set in the GPTMCTL register),
Timer B does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see . This
function is valid for one-shot, periodic, and PWM modes.
0
GPTM Timer B Match Interrupt Enable
Value Description
0 The match interrupt is disabled for match events. Additionally,
triggers to the DMA and ADC on match events are prevented.
1 An interrupt is generated when the match value in the
GPTMTBMATCHR register is reached in the one-shot and
periodic modes.
Note:
Clearing the TBMIE bit in the GPTMTBMR register
prevents assertion of µDMA or ADC requests
generated on a match event. Even if the TBTODMAEN
bit is set in the GPTMDMAEV register or the
TBTOADCEN bit is set in the GPTMADCEV register,
a µDMA or ADC match trigger is not sent to the µDMA
or ADC, respectively, when the TBMIE bit is clear.
June 18, 2014
Texas Instruments-Production Data
1115