TM4C129ENCZAD Datasheet, PDF (1193/2037 Pages) Texas Instruments – Tiva Microcontroller

Figure 18-5. Skewed Sampling
Tiva^™ TM4C129ENCZAD Microcontroller
ADC0 S1 S2 S3 S4 S5 S6 S7 S8
ADC1
S1 S2 S3 S4 S5 S6 S7 S8
18.3.2.7
Module Clocking
The ADC digital block is clocked by the system clock and the ADC analog block is clocked from a
separate conversion clock (ADC Clock). The ADC clock frequency can be up to 32 MHz to generate
a conversion rate of 2 Msps. A 16 MHz ADC clock provides a 1 Msps sampling rate. There are three
sources of the ADC clock:
■ Divided PLL VCO. The PLL VCO frequency can be configured to generate up to a 32-MHz clock
for a conversion rate of 2 Msps. The CS field in the ADCCC register must be programmed to
0x0 to select the PLL VCO and the CLKDIV field is used to set the appropriate clock divisor for
the desired frequency.
■ 16 MHz PIOSC. Using the PIOSC provides a conversion rate near 1 Msps. To use the PIOSC
to clock the ADC, first power up the PLL and then enable the PIOSC in the CS bit field in the
ADCCC register, then disable the PLL.
■ MOSC. The MOSC clock source must be 16 MHz for a 1 Msps conversion rate and 32 MHz for
a 2 Msps conversion rate.
The system clock must be at the same frequency or higher than the ADC clock. All ADC modules
share the same clock source to facilitate the synchronization of data samples between conversion
units, the selection and programming of which is provided by ADC0's ADCCC register. The ADC
modules do not run at different conversion rates.
18.3.2.8
Busy Status
The BUSY bit of the ADCACTSS register is used to indicate when the ADC is busy with a current
conversion. When there are no triggers pending which may start a new conversion in the immediate
cycle or next few cycles, the BUSY bit reads as 0. Software must read the status of the BUSY bit as
clear before disabling the ADC clock by writing to the Analog-to-Digital Converter Run Mode
Clock Gating Control (RCGCADC) register.
June 18, 2014
Texas Instruments-Production Data
1193