TM4C129ENCZAD Datasheet, PDF (1550/2037 Pages) Texas Instruments – Tiva Microcontroller

Ethernet Controller
Table 23-2. Enhanced Transmit Descriptor 0 (TDES0) (continued)
Bit
Description
11 LC: Loss of Carrier
When set, this bit indicates that Loss of Carrier occurred during frame transmission. This is valid only for the
frames transmitted without collision and when the MAC operates in half-duplex mode.
10 NC: No Carrier
When set, this bit indicates that the carrier sense signal form the PHY was not asserted during transmission.
9 LC: Late Collision
When set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision
window (64 byte times including Preamble in MII Mode). Not valid if Underflow Error (bit 1) is set.
8 Excessive Collision
When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to
transmit the current frame. If the Disable Retry (DR) bit in EMACCFG register is set, this bit is set after the first
collision and the transmission of the frame is aborted.
7 VF: VLAN Frame
When set, this bit indicates that the transmitted frame was a VLAN-type frame.
6:3 CC: Collision Count
This 4-bit counter value indicates the number of collisions occurring before the frame was transmitted. The count
is not valid when the Excessive Collision bit (TDES0[8]) is set.
2 ED: Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of over 24,288 bit
times (155,680 bits times when Jumbo Frame is enabled). This bit is dependent on the Deferral Check (DC) bit
being enabled in the EMACCFG register.
1 UF: Underflow Error
When set, this bit indicates that the MAC aborted the frame because the data arrived late from system memory.
Underflow Error indicates that the DMA encountered an empty Transmit Buffer while transmitting the frame. The
transmission process enters the suspended state and sets both Transmit Underflow (UNF) and Transmit Interrupt
(TI) bit in the EMACDMARIS register.
0 DB: Deferred Bit
This bit indicates the deferral mechanism is active and that the transmit state machine sends a JAM pattern to
defer reception when it senses a carrier before a normal transmission is scheduled. This bit is only valid in
half-duplex mode.
Table 23-3. Enhanced Transmit Descriptor 1 (TDES1)
Bit
31:29
Description
SAIC: SA Insertion Control
These bits request the MAC to add or replace the Source Address field in the Ethernet frame with the value
given in the MAC Address 0 register. If the Source Address field is modified in a frame, the MAC automatically
recalculates and replaces the CRC bytes.
The Bit 31 specifies the MAC Address Register (1 or 0) value that is used for Source Address insertion or
replacement. The following list describes the values of Bits[30:29]:
■ 0x0= Do not include the source address.
■ 0x1= Insert the source address. For reliable transmission, the application must provide frames without
source addresses.
■ 0x2= Replace the source address. For reliable transmission, the application must provide frames with
source addresses.
■ 0x3= Reserved
These bits are valid when the First Segment control bit (TDES0[28]) is set.
1550
Texas Instruments-Production Data
June 18, 2014