TM4C129ENCZAD Datasheet, PDF (71/2037 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCZAD Microcontroller
1.3.8.5
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
■ Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate
baud clock
I²C (see page 1408)
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I²C bus interfaces to external I²C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I²C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I²C bus can be designated as either a master or a slave. I²C module supports
both sending and receiving data as either a master or a slave and can operate simultaneously as
both a master and a slave. Both the I²C master and slave can generate interrupts.
The TM4C129ENCZAD microcontroller includes I²C modules with the following features:
■ Devices on the I²C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I²C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two 8-entry FIFOs for receive and transmit data
– FIFOs can be independently assigned to master or slave
■ Four transmission speeds:
– Standard (100 Kbps)
– Fast-mode (400 Kbps)
– Fast-mode plus (1 Mbps)
June 18, 2014
71
Texas Instruments-Production Data