TM4C129ENCZAD Datasheet, PDF (1687/2037 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129ENCZAD Microcontroller
Bit/Field
25
24
23
22:17
16
Name
AAL
8xPBL
USP
RPBL
FB
Type
RW
RW
RW
RW
RW
Reset
0
Description
Address Aligned Beats
Value Description
0x0 Address aligned transfers are not enabled.
0x1 If the FB bit is set, the internal bus interface generates all bursts
aligned to the start address least significant bits.
If the FB bit is 0, the first burst is not aligned but subsequent
bursts are aligned to the address.
0
8 x Programmable Burst Length (PBL) Mode
Value Description
0x0 8 x PBL mode is inactive.
0x1 Bit field RPBL and bit field PBL are multiplied 8 times. Therefore,
the DMA transfers the data in bursts of 8, 16, 32, 64, 128, and
256 words.
0
Use Separate Programmable Burst Length (PBL)
Value Description
0x0 The PBL value in bits[13:8] is applicable for both the RX and
TX DMA engines.
0x1 RX DMA is uses the RPBL bit field as its defined programmable
burst length and TX DMA uses the PBL bit field as its defined
programmable burst length.
0x1
RX DMA Programmable Burst Length (PBL)
When the USP bit is 1, this field is used to indicate the maximum number
of words to be transferred in one RX DMA transaction. This is the
maximum value that is used in a single block read or write.
The RX DMA always attempts to burst as specified in the RPBL bit each
time it starts a burst transfer on the system bus. The application can
program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value
results in undefined behavior. This field is valid and applicable only when
USP is set high.
0
Fixed Burst
This bit defines if burst is used during burs transfer operations.
Value Description
0x0 The DMA bursts the entire length during burst transfers except
for the last word, which is a single transfer.
0x1 The DMA uses only single, or fixed bursts incremented by 4, 8,
or 16 during normal bus transfers.
June 18, 2014
Texas Instruments-Production Data
1687